1. Field of the Invention
The present invention relates to a method of forming an embedded flash memory device. More particularly, the invention relates to a method of removing polysilicon residue in an embedded flash memory process without additional photolithography steps.
2. Description of the Related Art
Complementary metal oxide semiconductor (CMOS) memory can be divided into two main categories, random access memory (RAM) and read-only memory (ROM). Market demand for ROM has grown steadily in recent years and further growth is expected, particularly for flash memory in which any cell can be electrically programmed and a block, sector or page of cells can be electrically erased simultaneously. Flash memory offers greater flexibility than electrically programmable read-only memory (EPROM), as it is electrically programmable but erasable via ultraviolet exposure. Electrically erasable and programmable read-only memory (EEPROM) offers the advantage of being electrically erasable and programmable to the single byte, but is cost prohibitive and typically manufactured only for specific applications. In recent years, flash memory has found interesting applications in electrical consumer products such as, digital cameras, digital video cameras, cellular phones, laptop computers and Personal Digital Assistants (PDAs). Since mobility is a high priority for electrical consumer products, product size must be minimal. As a result, the capacity and functionality of flash memory modules must increase while size is reduced. The capacity of flash memory has increased from 4 to 256 MB and will increase up to 1 GB in the future.
In order to lower manufacturing cost, simplify the manufacturing procedures and increase operational speed for a semiconductor device, integrating different devices, such as a memory cell and a logic circuit on the same wafer has become a trend in semiconductor manufacturing. An example of such is an embedded flash memory device. The embedded flash memory cell comprises a flash memory cell and a logic circuit device formed on the same wafer.
FIGS. 1A to 1J are sectional views of a portion of a semiconductor substrate, schematically illustrating a conventional fabrication process for forming an embedded flash memory.
In FIG. 1A, a semiconductor substrate 100 comprising a memory area 102 and a logic circuit area 104 is provided. An isolation structure 106, such as an STI (shallow trench isolation), is formed in the substrate 100 to isolate the memory area 102, the logic circuit area 104 and active devices.
In FIG. 1A, by a known method disclosed in U.S. Pat. No. 6,429,075 or U.S. Publication No. 2002/0142545, a precursory flash memory structure 107 is formed on the substrate 100 in the memory area 102. The structure 107 includes a source region 108 formed in the substrate 100. A floating gate 110 is formed above part of the substrate 100, wherein an insulating layer 112 is formed therebetween. An insulating spacer 114 is formed on the floating gate 110. A conductive plug 116 electrically connects the source region 108 and is insulated from the floating gate 110 by an insulating layer 118. An oxide cap layer 120 is formed over the conductive plug 116. A conformal insulating layer 122 is formed on the sidewalls of the insulating spacer 114 and the floating gate 110. The conformal insulating layer 122 also expands to cover a portion of the substrate 100.
In FIG. 1B, a polysilicon layer (not shown) is formed on the insulating layer 122 to cover the structure 107. By performing a first photolithography procedure, the polysilicon layer (not shown) and the insulating layer 122 in the logic area 104 are removed to form a first polysilicon layer 130 over the substrate 100 in the memory area 102. The first polysilicon layer 130 is insulated from the substrate 100 by means of the insulating layer 122. During etching, it is difficult in practice to keep the sidewall of the first polysilicon layer 130 perpendicular to the substrate 100, thereby causing a polysilicon residue (162, as shown in FIG. 1H) to remain in subsequent steps. For example, the angle θ between the two planes is about 85˜87°.
In FIG. 1C, a first oxide layer 132 with a thickness of about 200 Å is blanketly formed overlying the substrate 100.
Referring to FIG. 1D, a process for defining an oxide layer with various thicknesses in the logic circuit area 104 is performed. In order to simplify the illustration, an oxide layer with two thicknesses is illustrated here. For example, by performing a second photolithography procedure and etching back the first oxide layer 132, a thick oxide layer 132 and a thin oxide layer 134 are formed in the logic circuit area 104. The thick oxide layer 132 can serve as the gate insulating layer for a high voltage MOS. The thin oxide layer 134 can serve as the gate insulating layer for a low voltage MOS. In FIG. 1D, a photoresist layer 136 covering the memory area 102 and part of the logic circuit area 104 serves as a mask layer in the photolithography procedure. Next, the photoresist layer 136 is stripped.
In FIG. 1E, a polysilicon layer (not shown) is conformally formed above the substrate 100. By performing a third photolithography procedure and anisotropic etching, part of the polysilicon layer (not shown) is removed to form gates 140, 140 in the logic area 104. Subsequent to this step (referred to as the MOS gate process), a first polysilicon residue 142 remains on the sidewall of the first oxide layer 132 on the first polysilicon layer 130.
In FIG. 1F, by performing a fourth photolithography procedure, a photoresist layer 150 is formed to cover the logic circuit area 104.
In FIG. 1G, the first polysilicon residue 142 is removed by isotropic etching. At this time, the first oxide layer 132 is also partially etched back to decrease the thickness thereof to about 100 Å.
In FIG. 1H, using the photoresist layer 150 as a mask, part of the first polysilicon layer 130 (including the first oxide layer 132 thereon) is removed by anisotropic etching. Thus, a control gate 160 is defined on the sidewall of the insulating spacer 114. The perpendicular thickness of the first oxide layer 132, however, is very thick and not perpendicular to the substrate 100 at the edge of the memory area 102, and causes a second polysilicon residue 162 to be left under the remaining oxide layer 132. Next, the photoresist layer 150 is removed.
In FIG. 1I, by performing a fifth photolithography procedure, a photoresist layer 170 is formed covering the memory area 102 and the logic area 104, but the second polysilicon residue 162 and the remaining oxide layer 132 above the isolation structure 106 are exposed.
Using the photoresist layer 170 as a mask, the unwanted second polysilicon residue 162 and the unwanted remaining oxide layer 132 are removed by isotropic etching. The photoresist layer 170 is then stripped, as shown as FIG. 1J.
In Fig. 1J, the insulating layer 122 adjacent to the control gate 160 is removed. Doped regions 172 and 174 are then formed in part of the substrate 100. Thus, a flash memory cell in the memory area 102 and MOS structures in logic area 104 are obtained. The doped region 172 serves as a drain region of the flash memory cell. The doped region 174 serves as a source/drain region of MOS.
According to the conventional method, an additional photolithography step is required to remove the second polysilicon residue 162 and the remaining oxide layer 132 above the isolation structure 106, thereby increasing manufacturing cost.
U.S. Pat. No. 6,429,075 discloses a process for forming a flash memory cell having a self-aligning floating gate. The method uses anisotropic etching to form a control gate beside an insulating spacer. Nevertheless, the method does not teach how to remove the polysilicon residue generated by the embedded flash memory process.
U.S. Patent Publication No. 2002/0142545 discloses a process for forming a self-aligned split gate flash memory cell. The method prevents short circuit or open circuits caused by misalignment during photolithography. Nevertheless, the method does not illustrate how to remove the polysilicon residue generated by the embedded flash memory process.
U.S. Pat. No. 6,265,267 discloses a fabrication method for an embedded flash memory device with various thicknesses of the gate oxide layers. The method prevents the gate oxide layer from damage during the removal of the photoresist, and forms the gate oxide layers with various thicknesses to accommodate demand for high and low voltage device operation. Nevertheless, the method does not teach how to remove the polysilicon residue generated by the embedded flash memory process.